ABSTRACT
As the CMOS technology advances, a digital-intensive design is essential for lowcost multistandard transceiver systems. The ΔΣ phase-locked loop (PLL) enables digital phase modulation without requiring digital-to-analog converters (DACs) and RF up-converters, thus significantly simplifying the overall transmitter architecture. Since the typical PLL bandwidth is not wide enough to accommodate the required modulation symbol rate, a digital compensation method [1-4] or a two-point modulation method is employed [5-15] to overcome the bandwidth limitation. In the digital compensation method, the transfer function of the digital compensation filter needs to be matched well with that of the PLL. However, the loop dynamics of the PLL is highly sensitive to process and temperature variations, making the digital compensation method less attractive for on-chip modulation. On the other hand, the two-point modulation method shown in Figure 17.1 overcomes the bandwidth control problem by having two modulation paths. The high-pass transfer characteristic of the voltage-controlled oscillator (VCO) modulation and the complementary low-pass transfer characteristic of the frequency divider modulation form an all-pass transfer function regardless of the PLL bandwidth. Accordingly, the PLL bandwidth can be
17.1 Introduction ..................................................................................................445 17.2 Hybrid-Loop Two-Point Modulator ..............................................................447
