ABSTRACT
Frequency synthesizer is an essential building block in wireless transceivers. Without a stable frequency reference, reliable communication cannot be established. As with other circuits in wireless transceivers, specifications of the frequency synthesizer are becoming more stringent with the introduction of advanced communication standards of high data rate. For example, long term evolution (LTE) using orthogonal frequency division multiplexing (OFDM) with multilevel QAM requires much lower phase noise than what was required for a 3G standard. In addition to noise, power consumption is another important, if not the most important, factor that needs to be considered. As with any other analog circuits, there exists relationship between
18.1 Introduction .................................................................................................. 467 18.2 Basics of PLL ................................................................................................468 18.3 Low-Noise Integer-N PLL Techniques ......................................................... 470
18.3.1 Injection-Locked Oscillator .............................................................. 470 18.3.2 Multiplying Delay-Locked Loop ...................................................... 472 18.3.3 Subsampling PLL ............................................................................. 472
18.4 Fractional-N PLL .......................................................................................... 473 18.5 Low-Noise Fractional-N PLL Using Noise Cancellation ............................. 475
18.5.1 Noise Cancellation in Voltage Domain ............................................ 475 18.5.2 Noise Cancellation in Phase Domain: Fractional Divider ................ 477
18.6 Low-Noise Fractional-N PLL Using High-OSR DSM ................................. 479 18.6.1 Fractional-N Frequency Synthesizer Using QNS ............................. 479 18.6.2 Fractional-N Frequency Synthesizer Using Nested PLL ..................480 18.6.3 Fractional-N Frequency Synthesizer Using Cascaded PLL ............. 482 18.6.4 Techniques for Low-Power DSM......................................................487
