ABSTRACT
Future high-performance computers require wide-band on-chip communication between memory and microprocessor cores. The global interconnect by top-layer metal in present CMOS technology has limited bandwidth and large crosstalk ratio [283, 284]. The lossy substrate with typical 10-Ω/cm resistivity introduces a low-impedance path between metal and substrate, resulting in narrow bandwidth and high loss. Moreover, at high operating frequency the current flow tends to crowd toward the surface of metal due to proximity effect, which leads to not only higher ohmic loss but also large electromagnetic coupling. As such, the CMOS metal-based interconnect is not scalable to provide wide bandwidth for on-chip communication beyond gigabit per second (Gbps) for one channel.
