ABSTRACT
Scaling has driven digital integrated circuit (IC) implementation from a design ow that uses primarily stand-alone synthesis, placement, and routing algorithms to an integrated construction and analysis ow for design closure. is chapter will outline how the challenges of rising interconnect delay led to a new way of thinking about and integrating design closure tools (see Chapter 13). Scaling challenges such as power, routability, variability, reliability, ever-increasing design size, and increasing analysis complexity will keep on challenging the current state of the art in design closure.
