ABSTRACT
One motivation for using regularity is the so-called timing closure problem, which arises because design ows are sequential and iterative; early steps need to predict what the later steps will accomplish. Inaccurate prediction leads to wrong decisions that can only be diagnosed later, resulting in many design iterations. In the deep submicron (DSM) domain, wiring delays dominate gate delays [1], thereby increasing the importance of obtaining good estimates of wiring eects early in the ow. Structured circuits, because of their layout regularity, allow more accurate area and timing estimation. Also, regularity provides better guarantees that the structured design layout is faithfully replicated in the fabrication. e reasons for this are subtle but can be summarized as follows. As the mask-making system approaches the physical limits of fabrication, the actual layout patterns on the wafer become dierent from those during design phases. To compensate these gaps, techniques like optical proximity correction (OPC) are used. However, the number of layout patterns generated by a conventional design ow can lead to OPC requiring an unreasonable amount of time and generating an enormous data set. Regular patterns from structured digital designs can reduce these requirements as well as reduce the discrepancies between the design and fabrication results by using fewer and simpler layout patterns.
