ABSTRACT
Further techniques for optimizing gate delays have a smaller impact on the end result compared to sizing and Vt-assignment and are, therefore, seldom used. First, the ratio of the p-type and n-type transistor sizes (β-ratio) is adjusted, trading o the rising and falling signal delay. Second, the sizes of serially connected transistors inside a gate are modied to balance the delays from dierent inputs to the output pin (tapering).
