ABSTRACT
Layout extraction is the translation of the topological layout back into the electrical circuit it is intended to represent. is extracted circuit is needed for various purposes, including simulation, timing analysis, and logic to layout comparison (see the Chapters on Digital and Analog Simulation, Timing Analysis, and Formal Verication). Each of these functions requires a slightly dierent representation of the circuit, resulting in the need for multiple layout extractions. In addition, there may be a postprocessing step of converting the device-level circuit into a gate-level circuit [97-101], but this is not considered part of the extraction process.
