ABSTRACT
This chapter deals with the design flows and associated frameworks for systems-on-programmable chip (SoPCs) systems, available for medium- and high-end field-programmable gate arrays (FPGAs). It discusses tools for multithread acceleration in high-performance computing (HPC) applications. Tools and methodologies for FPGA-based design have been continuously improving over the years in order for them to accommodate the new and extended functionality requirements imposed by increasingly demanding applications. Conventional synthesis tools were quite rapidly adopted by designers due to the productivity jump they enabled. Traditional or high-level synthesis (HLS) tools alone cannot support the design of many of today's complex FPGA embedded systems. In the last years, the main FPGA vendors are continuously releasing new specialized tools to ease the translation from OpenCL code into FPGA designs. These tools also provide ways for designs running in a host, usually a computer, to be accelerated by attaching one or more FPGA boards to it, often by means of PCI express (PCIe) connections.
