ABSTRACT
Over the past decade tremendous advances have been made in VLSI design. Greatly increased circuit complexity, however, continues to outpace engineers’ abilities to develop chips with up to half a million transistors. Conventional design methods have entailed teams of highly skilled and experienced engineers providing many months of effort. More recently, companies have been turning to logic synthesis tools to help alleviate market pressures that demand lower cost implementations with shorter development times. These tools allow less experi enced designers to develop application-specific ICs (ASICs), typically gate ar rays or standard cells. Further, the automated systems free a designer from the exploding number of details and provide greater time to examine high-level issues and experiment with various architectures. Thus, such tools increase pro ductivity and provide for better complexity management.
