ABSTRACT
Phase-lock loops are key building block of mixed-mode systems. They are at the heart of frequency synthesizers for data communications over wireless channels and clock and data recovery for data communications over wire channels. Charge-pump phase-locked loops, the most popular architecture of phase-locked loops, suffer from a number of drawbacks including high power consumption due to the need for charge pumps, rigid loop dynamics due to the finite frequency tuning range of the voltage-controlled oscillator (VCO) and RC filters, high silicon consumption due to the need for large capacitors in loop filters for filtering out transients present on the control voltage line of the VCOs, and charge-pump mismatch-induced reference spurs. A time-mode phase-locked loop is all-digital due to the replacement of its
8.1 Limitations of Charge-Pump Phase-Locked Loops .....................................302 8.1.1 Silicon Consumption ........................................................................303 8.1.2 Programmability ...............................................................................303 8.1.3Power Consumption ..........................................................................303 8.1.4 Spurs .................................................................................................304 8.1.5 Reference Spur ..................................................................................306
