ABSTRACT
As the International Technology Roadmap for Semiconductors (ITRS') [1] particle and other contamination requirements tighten with each successive technology generation, the cleaning of wafers becomes more complicated and more critical. For example, the 2003 version of the ITRS states that removal of <45 nm particles is one of the key challenges at the 90 nm node. Figure 1 shows the ITRS roadmap for particle size requirements for Front End of the Line (FEOL) and Back End of the Line (BEOL) processes.
