ABSTRACT
Optimum structures of floating body cell (FBC) for maximizing the signal are discussed. Two kinds of signal-to-noise ratios (SNRs) of FBC, one with respect to threshold voltage difference and the other with respect to cell current difference, are defined. It is shown that the latter generally provides more accurate index for predicting the yield of a memory using FBC. The minimum SNR which is necessary for making a multiple-gigabit memory functional is calculated. Hardware measurement results of SNR for a stateof-the-art FBC memory chip which demonstrate the validity of the theory and also satisfy the minimum SNR criteria will be given in Chapter 4.
