ABSTRACT
The operation principle of the ZnO NW FeFET is proposed schematically in Figs. 10.1 (c) and (d). When a negative gate voltage pulse is applied between the ZnO NW channel and the Pt gate (i.e., writing), the polarizations of the ferroelectric film will be aligned downward. After the gate voltage pulse is removed, the remnant polarization of the ferroelectrics introduces an effective negative field effect, which induces an equal amount of positive space charges within the NW (depletion). Therefore, an upward band bending at the
ZnO NW/Drain interface is established even when the applied gate voltage is zero or a small positive value, reducing the conductance of the NW. The cutting off the conductive channel of the n-type ZnO NW FeFET represents a binary “0” state of the memory device. Reversely, when a positive gate voltage pulse is applied, a binary “1” state is obtained. Thus a one-bit ferroelectric memory function is realized. FeFET allows nondestructive memory readout since the signal is read by detecting the conductance (or resistance) of the channel at zero gate voltage. The device has a nonvolatile nature due to the remnant polarization of the ferroelectric thin film, so that reading does not destroy the memory state.
