ABSTRACT
Figure 13.1 Cross section of a basic HEMT device. For large-scale integration (LSI)-type applications, ion-implanted source and drain regions similar to FETs were developed and used first [1, 2]; these could be self-aligned to a refractory gate that may be a pure refractory metal or a silicide-like WSix or a nitride like WNx, which are used as in the case of self-aligned FET processing. Annealing is needed for ion implant activation. However, annealing of epigrown structures with very thin layers and sharp profiles needed for good performance is not desirable. Therefore other schemes of reducing source and drain resistance have been devised, which mostly rely on use of epigrown, low-bandgap, heavily doped layers. The processing of such structures that do not employ ion implantation for n+ regions or for isolation is described first. Processing starts with alignment mark formation. These marks may be made by wet etching using standard peroxide-based etchants. The active areas where devices are to be formed must be isolated from each other by removal of conducting layers, thus forming mesa structures, as shown in Fig. 13.2. The requirements of this process step are not as critical as the ones for etching into the device channel area. Therefore dry etching could be used without any consequences of ion damage. Cap layers are next removed by patterning and etching to form source and drain regions and define the channel area in between. The next step is to form ohmic contacts. A photoresist mask is used to define the desired contacts and bond pads using a lift-off processing sequence. Au:Ge/Ni/Au-based metallization is deposited and lifted off to leave behind source-drain contacts and bond pads, etc. For a single recess, only one recess etch step is used. Photoresist patterning and wet etching steps are used
to define and etch off the GaAs cap layer and part of the AlGaAs layer. The etch depth is controlled to control the breakdown characteristics of the device. For a double-recessed device, a channel etch may be done first followed by a second recess. Next, the photolithography step is used to pattern the gate. Electron beam lithography may be needed for subhalf-micron gates. Wet etching is again used to etch off AlGaAs (or the GaAs layer for InGaAs channel devices). This etch step is the most critical for control of device parameters and must have good uniformity over the whole wafer. Spray etching systems may be needed for large-size wafers. Generally saturation current is measured to monitor the extent of the recess. Etching may be done in two or three steps, depending upon the degree of threshold voltage/Idss control that is desired. Etch stops may be grown in the epistructure to stop the recess etch for better Idss control and to avoid long process cycle time needed for multiple-recess etches. InGaP has excellent etch selectivity with respect to GaAs [3] and can be used as the etch stop layer and as a Schottky layer. Schottky gate metal is deposited using evaporation. A standard Ti/Pt/Au or Ti/Pd/Au metal sequence is used, the layers being optimized for desired reliability. The preclean prior to metal deposition is close-coupled to keep the surface clean and free of oxide and ensure good adhesion and good Schottky barrier characteristics. The gate metal may be used as the bottom plate of metal-insulator-metal (MIM) capacitors; therefore the deposition process must be optimized for low particles or nodules. The lift-off process must not leave flags, dog-ears, etc., over the gate fingers. Cross-sectional details of the gate and channel area are shown in Fig. 13.3. A transmission electron microscopy (TEM) cross section that shows the details of the channel region and the epilayers is shown in Fig. 13.4. Passivation silicon nitride is deposited next, again preceded by preclean. The details of the surface preparation before nitride deposition are critical to the performance, breakdown characteristics, and long-term stability of the devices. All contact openings must be patterned at this time for interconnect processing. If a plated metal layer is used for interconnect, a seed layer is deposited all over the wafer. This can be evaporated Ti/Au or sputtered TiW/Au. The wafers are patterned and can be electroplated in a bath or in an automated plating system. The thickness of the plating is generally several microns. After the
plating is complete, the resist is removed and the seed layer in between the metal lines is etched off. Mesa Formaon
Low insertion loss is important for PHEMT switch devices. For low insertion loss, device contact resistances must be minimized. Large energy band offsets between AlGaAs and GaAs can cause a discontinuity for electron transport in the contact path. Smaller band offsets were reported by several groups for InGaP/GaAs heterostructures [4, 5]. In0.48Ga0.52P has almost the same energy band gap as Al0.35Ga0.65As (~1.9 eV). Its advantages are fewer traps, less sensitivity to surface oxidation, and high wet etch selectivity. With the improved wet etch selectivity, recess etch uniformity below +/–10 Å can be achieved. The schematic layer structure for an InGaP/AlGaAs/InGaAs PHEMT is shown in Fig. 13.5 [6]. Device fabrication is similar to that described above for AlGaAs HEMTs, the four major steps being device isolation, ohmic contacts, recess etch, and Schottky metal gate deposition. For mesa isolation, wet etching
can be used to selectively remove the GaAs cap over the InGaP layer by using the H3PO4:H2O2:H2O (3:1:100) chemistry because this has excellent selectivity. HCl:H2O can be used to remove the InGaP layer and H3PO4-based chemistry to remove other epilayers. After the ohmic contacts are formed, these can be alloyed by rapid thermal processing (RTP) at a temperature near 400°C. For a gate recess, H3PO4:H2O2:H2O chemistry can again be used for selective etching. Special preclean steps are needed before the Schottky gate deposition. Figure 13.6 shows the layer structure and HEMT device structure in more detail. Good gate Schottky behavior, excellent drain-source I-V characteristics, high transconductance, and low insertion loss for switches have been demonstrated [3].
