ABSTRACT
Time interleaving a parallel array of slow analog-to-digital con-
verters (ADCs) is an effective approach to achieve high sampling
rate within a given process technology. The resulting system is
a time-interleaved ADC (TIADC). In this chapter, we first review
the parallel architecture of a TIADC and its associated speed
improvement. Despite the speed advantage, various technology-
dependent imperfections cause component mismatches among the
sub-ADCs and distort the output signal leading to degraded system
performance. In particular, the effects of offset, gain, timing, and
frequency response mismatches in both the time and frequency
domain are explained. Followed by that is a review of the techniques
published in the literature for estimating and correcting the
mismatch errors.
