ABSTRACT
In low power VLSI, scaling has the advantage of reduced size of chip with same specification. However, scaling of MOS devices has many challenges like leakage current, leakage power, read and write stability. Leakage power reduction and delay enhancement are main focus of this paper. The conventional 11T SRAM give external noise and high-power consumption as well as delay. 15T SRAM cell which has better write ability and improved read stability is proposed. Here, 15T SRAM cell has been compared with the existing 13T SRAM based on power consumption as well as delay calculation. For improvement of power consumption in SRAM cell the power gating technique is used. Computer simulation are done in is given in 180 nm technology using Cadence Virtuoso.
