ABSTRACT

Reuse-based System-on-Chip design using hardware intellectual property (IP) cores has become a pervasive practice in the industry. These IP cores usually come in the following three forms: synthesizable Register Transfer Level (RTL) descriptions in Hardware Description Languages (HDLs) (“Soft IP”); gate-level designs directly implementable in hardware (“Firm IP”); and GDS-II design database (“Hard IP”). The approach of designing complex systems by integrating tested, verified and reusable modules reduces the SoC design time and cost dramatically [73].