When an exception arises, ARM attempts to complete the current instruction, temporarily halts instruction processing, handles the exception, and then continues to process instructions.
The processor handles an exception by performing the following sequence of actions. 1. Save the current value of CPSR into the SPSR of the new operating mode for later
return. 2. Change to the operating mode corresponding to the exception. 3. Modify the CPSR of the new operating mode. Clear the T (Thumb) bit (bit 5) in
preparation for execution in ARM 32-bit mode. If an IRQ interrupt is present, set the I-bit (bit 7) to disable further IRQ interrupts. If an FIQ interrupt is present, set the F-bit (bit 6) and the I-bit (bit 7) to disable further FIQ interrupts.