PPENDIX ERVICE tx_interrupt_control
Pages 2

This value is processor-specific and is defined in the file tx_port.h. This value typically maps directly to the interrupt lockout/enable bits in the processor’s status register. The user must take care in selecting an appropriate value for new_posture. For the ARM processor, TX_INT_DISABLE corresponds to 0xC0 if both IRQ and FIQ interrupts are supported. If only IRQ interrupts are supported, the value is 0x80. The bits set correspond directly to the interrupt disable bits in the CPSR. TX_INT_ENABLE is 0, which clears all interrupt disable bits in the CPSR.