ABSTRACT
Contents 18.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 442 18.2 FPGA Hardware Task Scheduling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 444
18.2.1 Dynamic and Partial Reconfiguration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 444 18.2.2 Multitasking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 445 18.2.3 The Need for a Scheduler. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 445 18.2.4 Resource Placement Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 446
18.3 The Design of a Hardware Task Scheduler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 448 18.3.1 Reconfigurable Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 448 18.3.2 Task Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450 18.3.3 Runtime System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 451 18.3.4 Frequency Adaptive Hardware Task Scheduler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 452
18.3.4.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 452 18.3.4.2 Details of the Scheduler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 452
18.3.5 Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455 18.3.5.1 Simulation Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455 18.3.5.2 Trade Off between Execution Time and Energy
Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 456 18.3.5.3 Comparison with Existing Algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 457
18.4 Practical Illustration: Mobile Robots in a Wireless Sensor Network . . . . . . . . . . . . . . . . . . . . 459 18.4.1 SoPC-Based Mobile Robots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 459
18.4.1.1 Use of Mobile Robots in a Wireless Sensor Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 459
18.4.1.2 Prototype Design of a SoPC-Based Mobile Robot . . . . . . . . . . . . . . . . . . 460 18.4.2 Image Processing Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 462
18.4.2.1 Application Scenario . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 462 18.4.2.2 Implementation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 463
18.5 Conclusions and Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 464 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 465
18.1 Introduction The regular structure of field programmable gate arrays (FPGAs) enables the utilization of massively parallel circuit design for hardware acceleration of software tasks. Specifically, we can offload some computation-intensive tasks in software applications, which are originally executed in the instruction set processor, to FPGAs so as to increase the overall system efficiency. Specifically, an FPGA-based system offers the following advantages over a traditional processor-based system:
Computation efficiency: FPGAs, a kind of (re)programmable chips, have traditionally been used for hardware prototyping or as glue logic for connecting different components in a system. With today’s advanced chip technology, FPGAs’ gates are clocked at high rate and of high density and have abundant dedicated hardware resources, which brings about an amazing computer architecture for high performance computing-reconfigurable computing. FPGAs can typically achieve 20-100 speedup factors over processors.
