ABSTRACT
This chapter introduces a low-power conceptual design for a distributed architecture of a single passive sensor processor. It introduces and elaborates the key concepts of the low-power design of the wireless passive sensor network (WPSN) node processor. The novel low-power techniques described in the following sections are applicable not only to WPSN but also to RF identification (RFID) systems and RFID sensor networks. A significant contribution toward achieving a low-power sensor node processor is introduced in this chapter that highlights customizing a processor based on its subset instruction set architecture (ISA) for the specific target application. The commonly used 8051 microcontroller in sensor nodes will be considered as an example for exploring its ISA and its application to the proposed conceptual distributed design. The highlevel data-driven design flow will be described in this section that requires minimum changes to a traditional synchronous flow.
