ABSTRACT
During the last two decades, there have been enormous efforts in minimizing the energy consumption of CMOS circuit systems. Dynamic voltage scaling (DVS), involving dynamic adjustments of the supply voltage and the corresponding operating clock frequency, has emerged as one of the most effective energy minimization techniques. The one-to-one correspondence between the supply voltage and the clock frequency in CMOS circuits imposes an inherent constraint on DVS techniques to ensure that voltage adjustments do not violate the target system’s timing (or deadline) constraint.
