Energy-Eﬃcient Network-on-Chip Architectures for Multi-Core Systems
Modern large-scale computing systems, such as data centers and high-performance computing (HPC) clusters are severely constrained by power and cooling costs for solving extreme-scale (or exascale) problems. This increasing power consumption is of growing concern due to several reasons, for example, cost, reliability, scalability, and environmental impact. A report from the Environmental Protection Agency (EPA) indicates that the nation’s servers and data centers alone used about 1.5% of the total national energy consumed per year, for a cost of approximately $4.5 billion. The growing energy demands in data centers andHPCclusters are of utmost concern and there is a need to build eﬃcient and sustainable computing environments that reduce the negative environmental impacts. On the other hand, continuing progress and integration levels in silicon technologiesmakepossible complete end-user systemson a single chip. This massive level of integration makes modern multi-core chips all pervasive in domains ranging from weather forecasting and astronomical data analysis to consumer electronics, smart phones, and biological applications. Consequently, designing multi-core chips for exascale computing is perceived to be a promising alternative to traditional cluster-based solutions. As an example, driven by massive parallelism and extreme-scale integration, Intel has recently created an experimental “single-chip cloud computer” targeting energy-eﬃcient HPC applications.