chapter  3
18 Pages

- The SPARC Processor Architecture

BySimone Secchi, Antonino Tumeo, Oreste Villa

The SPARC (Scalable Processor ARChitecture) instruction set architecture is one of the most employed RISC design for multicore processors.

The first 32-bit version of the architecture was introduced in 1986 with the name SPARC Version 7 (SPARCv7). In 1990, the next revision, SPARCv8, introduced integer multiply and divide instructions [1]. The current major revision, SPARCv9, moved the specification from a 32-to a 64-bit architecture [2]. Originally presented in 1993, the SPARCv9 architecture has since then been extended to support chip multithreading (CMT), hyperpriviliged processor instructions and mode of execution, SIMD extensions [3, 4, 5].