ABSTRACT
Even recently, Sustainable Development (SD) was only the concern of green groups. However, today, SD has become a paramount issue and an aspiration of long-term civilization development of human beings since “Resolution 42/187 of the United Nations General Assembly” was passed in December 1987. The Brundtland Commission of the United Nations defined SD as the development that “meets the needs of the present without compromising the ability of future generations to meet their own needs” [1]. From then on, several United Nations’ Conferences (from Rio de Janeiro-1992 to Durban-2011) confirmed this important issue. One of the most obvious aspects and challenges of SD is the Earth climate change and the ever-growing CO2 emission. Currently, 3% of the world-wide energy is consumed by the ICT (Information and Communications Technology) infrastructure, which causes about 2% of the world-wide CO2 emissions and surprisingly is comparable to the worldwide CO2 emissions due to all commercial airplanes. The ICT sector’s carbon footprint is expected to quickly grow to 1.4 Giga ton CO2 equivalents by 2020, nearly 2.7% of the overall carbon footprint from all human activities [2]. These values of carbon footprint are extremely impressive. They have been confirmed by a lot of scientific studies and reported in many relevant international conferences and workshops, such as the ”Next Generation Wireless Green Networks Workshop” held in SUPELEC in November 2009 [3]. Basically, one should deal with the fundamental challenges with a twofold aim, in order to attempt to solve these problems:
• Decrease the ICT footprint itself, • Use ICT so as to decrease the “human beings” activities footprint. This chapter deals with electronics power consumption in nanoscale CMOS
technology. Traditionally the Integrated Circuit (IC)’s power consumption was due to dynamic power consumption. Consequently, in order to decrease frequency while increasing ICs throughput, the solution was to parallelize processes. Nevertheless one of the most significant power related subjects that arose recently is static power leakage due to the leakage current. It was stated in [4] that the leakage power consumption is strongly correlated to the circuit area. Therefore a new trade-off between parallelism and power consumption should be found. This was discussed, for example, in [5]. Leakage power represents a significant share of the total power dissipation especially for 65nm technology and below. A lot of papers are dealing with leakage power consumption itself within the framework of nanoscale technology [4, 6]. If, in the
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past, FPGAs were mainly concerned with dynamic power consumption [7], it remains no more true with new technologies (65nm and below) [8] and with the large number of transistors inside a FPGA circuit: the leakage power consumption becomes more and more important both in the used and unused part of the component. Section 2 will give more details on power consumption origins. A lot of works carried out in the recent years studied ways to reduce leakage power consumption in CMOS [9-11] and particularly for FPGA [12,13].
