ABSTRACT
Along with the Digital Signal Processor (DSP) and Field Programmable Gate Array (FPGA) development, the use of DSP+FPGA embedded hardware system is showing its superiority. Data communication performance between DSP and FPGA processor is one of the major problems aecting the whole performance of embedded systems, thus communication between FPGA and DSP has become the key of the whole system design. At present, there are a variety of schemes for implementation of communication between FPGA and the DSP, including external memory interface such as EMIF scheme, host interface such as HPI scheme, serial type interface such as McBSP scheme, and special interface such as RapidIO scheme. This paper will focus on the above common implementation scheme, take TI company’s DSP processor and Xilinx company’s FPGA processor as an example, make an analysis from the circuit, the communication rate, logic control, resource occupation, hardware cost, applicable situation and other aspects, gave the recommendation on the system design scheme selection.
