A 4-bit array multiplier design by reversible logic

With the development of mobile computing, the low power design becomes increasingly important in integrated circuits. Thus, more and more concern falls on energy dissipation. However, energy dissipation in irreversible logic design is inevitable, which is explained by Landauer’s principle-kTln2 joules of heat energy will be generated once erasing each bit of information [1]. One of the solutions is designing the circuits by reversible logic.