ABSTRACT
Very high speed analog to digital converters (ADCs) with sampling rate which higher than 1GSPS are widely used in software defined radio (SDR), high speed oscilloscopes, wireless communications testers, etc. Such a high speed ADC can be implemented by using full flash ADC architecture, or pipelined ADC architecture or time-interleaved architecture, but the most popular one is folding and interpolating ADC architecture. A 5bits full flash ADC using conventional architecture in Li’s work needs at least 25 − 1 or 31 comparators, which cost a large chip area and consume a great power dissipation. The conventional continuous-time folding amplifiers utilized in Hai’s and K’s works also has frequency multiplication problem, which deteriorated the performance of folding amplifiers.
