ABSTRACT
Arithmetic Logic Unit (ALU) is an advanced circuit that performs math operations like addition, subtraction, multiplication and division, logical operations, shift and rotate operations. Fast processing performance of ALU depends to a great extent on the multipliers. Multipliers are multifaceted units and play a significant task in deciding the overall area, speed and power consumption of digital circuits. The optimization of speed, power, and area of the multiplier is an important design problem. In this work the Hardware Description Language code is implemented for different types of multiplier blocks, simulated using Cadence IUS simulator and synthesized by the RTL Compiler.
