ABSTRACT
In this paper, an area efficient low power design of memoryless distributed arithmetic based Least mean square adaptive filter has been proposed. The throughput is increased because of computing the inner product and simultaneously implementing in weight-increment operation. Here we have proposed two memoryless design of distributed arithmetic (DA) unit. First Design uses 2:1 multiplexers and second design uses Onboard Credential (ObC) architecture to replace Look Up Table (LUT) of the conventional DA to reduce the overall area of the filter. Enhanced compressor adder is used for accumulation of the partial products, which further helps to reduce the area. Parallel updating of the generation and accumulation enhance the throughput of the design. The proposed designs require more than half area that required for the existing LUT based inner product block. The synthesis result shows that the area reduced by 52.79% and also the MUX based DA for the Adaptive filter causes 69.25% less power consumption for filter tap: N = 16, 32 and 64. Proposed design provides 36.50% less Area Delay Product (ADP).
