Design-Time Tooling to Guide Programming for Embedded Heterogeneous Hardware Platforms
Heterogeneous hardware platforms are now available in many devices. However, their remain extremely complex to program and it is even harder to exploit the power of heterogeneous hardware platforms adequately. Tools for assisting analysts-developers at design time to make efficient design space exploration for better exploiting heterogeneous hardware architecture are therefore truly needed. This work presents Placer, a model-based tool for optimizing the mapping, i.e., placement and scheduling, of task-based software onto heterogeneous hardware and DS-Explorer for rapidly prototyping software tasks offloading on FPGA and obtain static and dynamic properties of software tasks execution on FPGA. Placer and DS-Explorer are not implemented from scratch. They respectively leverage on existing tools Quickplay from Accelize and OscaR by UCL and CETIC. An application of both tools, Placer and DS-Explorer is demonstrated on an Industry use case named Aquascan provided by Deltatec.