ABSTRACT
Design in complementary metal oxide semiconductor (CMOS) is considerably more challenging than with bipolar transistors. Semiconductor technologies are usually referred to by the lithography node, designated by its minimum feature length, for example, 90 nm CMOS. Bipolar transistors, particularly silicon germanium heterostructure bipolar transistors (HBT) implemented in bipolar/CMOS (BiCMOS) technologies, have dominated the market in chip designs for wireless applications. The chapter introduces a model methodology for capturing process variation in scaled CMOS technologies. It considers potential cost reductions when migrating applications from BiCMOS to CMOS. The single most compelling argument for using CMOS to implement wireless applications is integration density. It is likely that competitive pressure will dictate that wireless applications, which can be implemented with acceptable performance in CMOS, will be implemented in CMOS. Relative process simplicity and high manufacturing capacity contribute to lower die cost of CMOS when compared to BiCMOS or compound semiconductor technologies.
