ABSTRACT

This chapter describes basics of simulation and its categorization into logic and fault simulation. The importance of fault simulation algorithms before actual testing on hardware is explained. Evolution of algorithms for reducing test time from simplest serial to differential fault simulation algorithm is described by explaining each algorithm. Identification of test vectors by fault simulation makes it different from logic simulation in which all possible inputs are applied for functionality verification. The concept of fault simulation is further practically implemented using Verilog language in which parallel and concurrent algorithms are implemented and simulation results in terms of waveforms are explained for better understanding.