ABSTRACT
The complexity of circuit design keeps increasing rapidly, and to keep up with the design viability, economics, and timely production, design engineers have turned their attention to tools that allows design entry, verification, and testing of their products with a minimum amount of time and cost. Description of the architecture and the functionality of discrete electronic systems has become a reality with the advent of hardware description languages (HDLs). The importance of these tools in integrated circuit design methodology includes its capability for simulation, synthesis, and netlist generation. These languages have proved to be an indispensible tool in high complexity circuit designed by allowing the transformation of the design specification to mask layout for transistor fabrication, verification, and testing. This chapter deals with the basics of Verilog and its variants, its use for both digital and analog designs, and different modeling approaches including mixed modeling. Test benches are an important construct of HDLs that allows for verification of the design through simulation. Verilog-A, the analog counterpart of Verilog, models analog circuits, whereas the Verilog-AMS allows for the design of mixed-signal modules.
