ABSTRACT

This chapter presents a new switch architecture and a performance study. Asynchronous transfer mode (ATM) switch buffer design is one important study issue and head-of-line (HOL) blocking is another. The chapter reports a new crosspoint switch reducing the probability of HOL blocking. It provides the study on the input buffer type switch with window policy. Performance is examined in very fine detail under uniform and non-uniform traffic. The chapter reports delay and performance of asynchronous transfer mode adaptation layer 2 (AAL2) used for low bit-rate voice service. It describes AAL2 switch performance in terms of cell delay, cell loss, link bandwidth, and link efficiency (load). A new jitter-controlled traffic scheduling algorithm that provides an upper bound for the delay jitter in case of rate-controlled connection, such as packet video streams and Internet protocol telephony, is proposed. It guarantees bounded delay and worst-case fair weighted fairness. Available Bit Rate service is standardized to handle applications of data traffic in ATM network.