ABSTRACT

This chapter summarizes the examples of the automated transmission line pulse (TLP) for safe operating area (SOA); conventional, high-voltage, and transient latch-up (TLU) cases; statistical analysis of the process capability index; and system-level electrostatic discharge (ESD) intellectual property (IP) development. Technology computer-aided design (TCAD) methods utilized properly within the well-understood limits of their physical applicability enable the highly efficient ESD system and chip co-design approach. The chapter addresses the requirements for highly integrated SoC/SoP power-efficient analog integrated circuits (ICs) with accurate physical design using mixed-mode simulation. Creation of the parameterized device templates and parameterized process descriptions for each technology is a one-time investment, which enables a new level of design automation. Using the parameterized approach, the finite-element model (FEM) structure with desired parameters is automatically 'assembled' at the beginning of each mixed-mode simulation run using the defined desired parameter values.