Design of Component-Level On-Chip ESD Protection for Integrated Circuits
This chapter presents an overview of integrated circuit (IC) protection design methods that involve various clamps based on the protection needs to meet the design applications. An overall systematic approach is to identify the design targets and formulate a strategy for the different types of pins being protected. These could be input, output, bidirectional, and power pins. Further, thinner gate-oxide inputs face restriction of the voltage rise at the gate from the discharge current through the ESD clamp's on-resistance and may force lowering the expected ESD levels. High-speed inputs and radio-frequency (RF) I/Os fall into these categories. In formulating the protection strategy, any type of intuitive design is undesirable as it is often guaranteed not to work consistently. An empirical method using data from test structures is a practical and safe approach. There are essentially two types of protection design styles: local clamp approach and rail clamp approach.