ESD, EOS, and Latch-Up Test Methods and Associated Reliability Concerns
This chapter covers the primary test methods used to evaluate integrated circuit (IC) robustness to electrostatic discharge (ESD), transient overstress, and latch-up events. It also describes reliability issues relating to these short-duration electrical events. There are three main mechanisms producing high-energy/short-duration electrically induced damage in ICs: ESD, the more general electrical transients, and latch-up. Other electrical transients (separate from ESD) refer to those caused by any nontriboelectric or non-electric field-induced electrical overstress (EOS) mechanism, and particularly those over 1 µs in duration. The chapter discusses reliability of ESD tested product, including the snapback mechanism. Finally, ESD and EOS impacts on reliability, along with suggested guidelines for minimization. There are three widely used ESD models describing different energy transmissions of the ESD event for IC components: the HBM, the CDM, and the machine model (MM).