Design of Power-Rail ESD Clamp Circuits with Gate-Leakage Consideration in Nanoscale CMOS Technology
Electrostatic discharge (ESD) phenomenon is a charge flow when two objects with different voltage potentials reach contact. Such ESD events can cause serious damage to the integrated circuit (IC) products, during assembly, testing, and manufacturing. In advanced nanoscale CMOS technology, there are two commonly used processes provided from foundry for some specified purposes. They are low-power (LP) and general-purpose (GP) processes. The chapter summarizes comparison among various power-rail ESD clamp circuits. Recently, some circuit techniques have been developed to reduce the gate-leakage current and layout area of the power-rail ESD clamp circuits. In this chapter, those different circuit techniques are reviewed and discussed. The layout area, ESD robustness, and standby leakage current among those designs are compared. Metal oxide metal (MOM) capacitors have been commonly used in IC design because the MOM capacitor has higher linearity, higher quality factor (Q), small temperature variation, and almost no leakage current.