ESD Protection Circuits Using NMOS Parasitic Bipolar Transistor
This chapter describes the case when an NMOS parasitic bipolar transistor is used in electrostatic discharge (ESD) protection circuit. It also describes method to improve ESD robustness by boron ion implantation under the drain contact area without degrading the AC characteristics of the circuit. To improve ESD robustness, it is effective to increase substrate resistance by reducing the doping concentration of the substrate under the epitaxial substrate (Epi). The chapter further describes PMOS ESD protection circuit using circuit diagram, cross-sectional view, and current-voltage (I–V) characteristic. It is important to understand ESD design window for ESD protection design. Important points of ESD design are as follows: understand the discharge capability of the ESD protection circuit, provide low-resistance discharge paths for ESD surge current, and before starting the ESD design, check failure voltage of protected circuits.