ABSTRACT
From the complementary metal-oxide-semiconductor (CMOS) technology node beyond 90 nm, it has become very difficult to improve device performance by only reducing the physical gate length. According to the International Technology Roadmap for Semiconductors [1], by the year 2015, the channel length of metal-oxide-semiconductor field-effect transistors (MOSFETs) is projected to be less than 10 nm. The historic performance enhancement trend can probably continue until the 11 nm node with physical gate length no shorter than 10 nm. The logic technology node and physical gate length as a function of year of introduction are shown in Figure 5.1. For instance, at the technology nodes of 130 and 90 nm, the physical gate lengths are reduced to ~70 and ~50 nm, respectively. At the end of this decade, the difference in the physical gate length and the technology node could reach as much as 50%. It may be noted that beyond the 130 nm node, the scale of the physical gate length has entered into the nanometer regime. The challenge of fabricating such gate length lies in a much higher level of integration. There have been reports suggesting that the fundamental limit of scaling is at or near a gate length of 25 nm. Following Moore’s law is becoming extremely difficult for the upcoming technology nodes, where the main challenging point for device scaling is the off-state leakage current. Planar MOSFETs with gate lengths as short as 5 nm have been fabricated; however, owing to huge off-state currents, they are not suitable for future integrated circuits (ICs).
