ABSTRACT
The planar device architecture of conventional metal-oxide-semiconductor field-effect transistors (MOSFETs) is limited to scaling beyond 15 nm gate length due to transistor switching criteria. Complementary metaloxide-semiconductor (CMOS) technology has been scaled during the past 30 years with a drive to continuously increase the density of devices on a chip and increase the switching performance of transistors, the major components of electronic circuits. Toward the end of the ITRS road map [1], in which the channel length is predicted to be aggressively scaled, careful device design consideration is required due to trade-offs between device current drive, short-channel effects, and power consumption. The on-state current (Ion) of a MOSFET is represented by
I W Q V v V C V V v V/ ( ) ( ) ( ) ( )on s DD DD G DD th DD= ≈ − (6.1)
where W is the device’s width, VDD is the power supply voltage, Vth is threshold voltage, Qs is the inversion charge density, and v is the velocity near the source region (injection velocity). The power consumption, Pdiss, can be approximated by [2]
P P P fC V V I I 10diss D S L DD DD leak th
= + = α + +
(6.2)
where PD, PS, α, f, CL, and S are dynamic power dissipation, static power dissipation, activity factor, operating frequency, load capacitance, and subthreshold slope, respectively, and Ileak represents the total leakage current from gate and junction sources, and Ith is the drain current at Vth. In order to maintain low power consumption and lower VDD and leakage current, higher Vth and steeper S are required according to Equation (6.2). On the other hand, large gate capacitance, low Vth, and high velocity are required to achieve a high performance in terms of Ion. In addition to the trade-offs for Vth and VDD, the
choice of high CG requires a thinner dielectric, which can increase direct tunneling, which enhances the leakage and increases the power consumption. From the electrostatics point of view, high substrate doping is required for aggressively scaled planar devices to control the short-channel effects. The high doping results in increased junction and gate-induced drain lowering (GIDL) degraded on current due to the increased Coulombic scattering and increased variation in threshold voltage. In addition, extension and halo implants needed to control short-channel effects increase source/drain parasitic series resistance, which degrades the current drive. Considering the trade-off between the current drive, short-channel effects, and power consumption, conventional Si MOSFETs fail to satisfy the device requirements that call for new materials and device architectures for future CMOS generations. To enhance the current drive, new channel materials such as strained Si, SiC, SiGe, Ge, and III-V have been extensively investigated over the past 20 years. Uniaxially strained Si technology with tensile liner and embedded SiGe stressors was incorporated into mainstream CMOS production starting at the 90 nm technology node. To further continue scaling and improve the current drive high-permittivity-dielectric (high-κ)/metal gate technology has also been commercialised by Intel in the 45 nm technology node. This has been shown to dramatically improve the gate leakage and power consumption for both n-and p-MOSFET devices. Ultra-thin-body and multigate SOI devices have been shown to provide excellent scalability and immunity to short-channel effects. The geometry enables excellent electrostatic control by the gate, and the lightly doped Si channel dramatically reduces the random dopant fluctuation and Vth variation. In addition, these device architectures benefit from lower capacitive parasitic and junction leakage due to the presence of a thick buried oxide. Among various options for multigate device architecture, such as double-gate, tri-gate, etc., the nanowire (NW) channel with a wraparound gate, so called gate-all-around (GAA), has the largest advantage in terms of electrostatic integrity. However, several undesired effects become prominent from the miniaturisation of the device dimensions. One such unwanted effect is a strong increase of the lowfrequency noise generated in the transistor as the size of the device decreases. Moreover, there are many unexplored issues regarding the introduction of new materials in complementary metal-oxide-semiconductor (CMOS) technology. Therefore, electrical evaluations of devices using new materials and architectures are highly desired.
