ABSTRACT
As complementary metal-oxide-semiconductor (CMOS) downscaling approaches the manufacturing limits, process variability and reliability degradation become the key limiting factors for future integrated circuits and systems design. At nanoscale, physical factors that previously had little or no impact on circuit performance are now becoming increasingly significant. Examples include process variations, transistor mobility degradation, and power consumption. These new effects pose dramatic challenges to robust circuit design and system integration. Process variations have become increasingly important for scaled technologies starting at 45 nm, as nontraditional materials and structures and even strain technology are being introduced to enhance the device performance. Use of strain technology in manufacturing has urged that the designers assess layout-dependent effects and manage their impact. Thus, the demand of predictive modelling becomes even stronger as we face more complicated and diverse technological choices for larger-scale integration. High process variability not only affects the circuit performance but also reduces manufacturing yield. To improve manufacturing yield of technologies 45 nm and below, performance variability should be considered during the design phase. In the conventional design approach, high variability leads to overdesigning, thereby increasing area and power consumption. To avoid overdesigning, accurate estimation of variability is required.
