ABSTRACT
The decrease in device size or scaling into deep submicron feature sizes has introduced many design challenges that did not exist before or many of which could be ignored. Some of the deep submicron issues are exponential increase in leakage power, thermal issues and hot spots on the chip due to increasing transistor density, deterioration in reliability due to increase in various types of noise (e.g., cross-coupling noise, power grid noise), soft errors due to cosmic radiation and continuous scaling of supply voltage, and fabrication defects. Advanced semiconductor manufacturing technology demands techniques for efficiently designing high-performance, low-power integrated circuits, with shorter time-to-market design time [1]. It is necessary to link manufacturing variation information back to design, enabling custom integrated circuit (IC) designers to optimise layouts and maximise yields. The main challenges in manufacturing are reducing cycle time, enhancing production quality and variability control, improving equipment productivity, reducing the environmental impact, supporting heterogeneous integration, advancing system integration, and functionalising packaging. The merging of “beyond CMOS” and advanced “more than Moore” devices and processes to create a complementary metal-oxide-semiconductor (CMOS) backbone will further increase process variability and other reliability issues. Thus, the need for new device/circuit architectures, metrology, and characterisation techniques will increase.
