ABSTRACT
For more than four decades the rapid progress in complementary metaloxide-semiconductor (CMOS) technology has taken place through the tremendous pace of scaling, leading to an enormous increase in speed and functionality of electronic devices. However, it is getting extremely difficult to meet metal-oxide-semiconductor field-effect transistor (MOSFET) performance gains with acceptable device leakage. Now the gate leakage current constitutes a major part of the power budget of microprocessors. Another critical scaling issue involved is the increase of the source/drain series resistance resulting from the ultra-shallow p-n junctions in the source/drain regions. To keep the source/drain series resistance at a reasonable fraction of the total channel resistance (~10%), several alternative MOSFET structures have been proposed, such as nonoverlapped gate structures, which do not require ultra-shallow source/drain junctions or structures with metallic source and drain electrodes to minimise the series resistance. Advanced multigate structures, such as FinFETs and ultra-thin-body (UTB) MOSFETs, may provide a path toward scaling CMOS to the end of the ITRS road map. Stress and strain engineering are the key elements in current CMOS technologies and can accommodate nonclassical CMOS structures.
