ABSTRACT
This chapter describes the approaches for optimization of semiconductor device fabrication processes and structures to mitigate radiation effects in advanced silicon-based technologies, primarily complementary metal oxide semiconductor (CMOS). It discusses effects and mitigation approaches related to insulators, active device regions, and process integration considerations that may enable radiation hardening by design techniques to be applied for single-event hardening. Ionizing radiation can result in bulk trapped charge and interface states in insulators. The cumulative effects, referred to as total ionizing dose (TID) effects, alter device parameters. The main consideration for TID effects in advanced bulk CMOS devices is charge trapping in the shallow trench isolation, particularly activation of the parasitic sidewall device for intra-device leakage. The dominant impact of TID arises due to a difference in the mobility and trapping of electrons and holes, resulting in an imbalance in trapped charge, typically net positive.
