ABSTRACT
This chapter presents techniques and architectures that are applicable to either passive or active tags, or both. These techniques are designed to address the concerns of reducing power in Radio frequency identification device (RFID) systems without compromising their capability or to extend their capability in a power-efficient manner. The chapter provides a technique to significantly increase the memory capacity of a passive tag while minimizing the amount of additional energy required. It describes a power macromodeling technique that works in concert with the RFID design automation flow and examines the effective evaluation of alternate protocol designs. The chapter discusses the design and evaluation of a passive active RFID tag that has many of the benefits of an active tag that uses considerably less energy. It explores a passive switch for an active transceiver called the burst switch and a power-aware packet storage and filtering technique called the smart buffer.
