Memory Organization for Low-Energy Embedded Systems
This chapter focuses on methods that aim at reducing the energy consumption by optimizing the memory hierarchy and on techniques that target the reduction of the energy consumed in memory transfers. It provides several effective memory partitioning approaches, especially focusing on methods that are suitable to be used in an automatic fashion, and discusses solutions for information compression including both code and data. Numerous code compression techniques have been proposed for reducing instruction memory size in low-cost embedded applications. The original machine code can thus be compressed to reduce the memory bandwidth that is needed to execute the program. The chapter presents a number of approaches that target the reduction of the memory-processor traffic and, as a consequence, the number of accesses to memory locations, exploiting memory compression. Optimizing the processor-to-memory bandwidth is one possibility to simultaneously reduce memory and bus energy.