FPGA Synthesis and Physical Design
This chapter describes computer aided design (CAD) for programmable logic not just from an individual algorithm perspective, but in the context of the end-to-end flow that a designer using a commercial Field-programmable logic array (FPGA) would experience. It analyses algorithms, tools, and techniques for both the end-user and architecture-development FPGA CAD flows. The physical design aspect of FPGA tools consists of clustering, placement, physical re-synthesis and routing. One major difference between standard and FPGA synthesis is in cost metrics. The target technology in a standard cell application specific integrated circuits (ASIC) library is a more finely grained cell while a typical FPGA cell is a generic k-input look-up table (LUT). Subfactor extraction algorithms are much more important for FPGA synthesis than commonly reported in academic literature where ASIC gates are assumed. An interesting recent development in FPGA synthesis is the use of sets of pairs of functions to be distinguished for exploiting the inherent flexibility in LUT-based netlists.