ABSTRACT
Static timing analysis (STA) plays a vital role in facilitating the fast and reasonably accurate measurement of circuit timing. This chapter provides an overview some of the most prominent techniques for STA. It outlines issues related to Statistical Static Timing Analysis, a procedure that is becoming increasingly necessary to handle the complexities of process and environmental variations in integrated circuits. The chapter presents techniques that are used for the STA of digital combinational circuits. The word “static” alludes to the fact that this timing analysis is carried out in an input-independent manner, and purports to find the worst-case delay of the circuit over all possible input combinations. Unlike interdie variations, whose effects can be captured by a small number of STA runs at the process corners, a more sophisticated approach is called for in dealing with intradie variations. This requires an extension of traditional STA techniques to move beyond their deterministic nature.
